This invention relates in general to a system, apparatus, and method comprises one or more mapping and modeling systems used for power estimation, management, and improved efficiencies for the integrated circuit. In addition, the invention provides a feedback telemetry and actuation system, apparatus, and method for controlling the flow speed and temperature of coolant fluid over an integrated circuit.
Power is a major design challenge for chip architects due to its limiting nature on the performance on semiconductor-based chips. Modern multi-core processors designs are highly complex, incorporating a number of independent cores with billions of transistors. This complexity makes accurate pre-silicon power modeling a very difficult task. Furthermore, workloads and process variability alter the power consumption during runtime, making it harder to accurately estimate power consumption during design time.
In recent years, post-silicon power mapping has emerged as a technique to mitigate the uncertainties in design-time power models and enable effective post-silicon power characterization. Many of these techniques rely on inverting the thermal emissions captured from an operational chip into a power profile. However, this approach faces numerous challenges, such as, the need for accurate thermal to power modeling, the need to remove artifacts introduced by the experimental setup, where infrared transparent oil-based heat removal system can lead to incorrect thermal profiles, and leakage variabilities.
Post-silicon power mapping for multi-core processors is the process of reconstructing power dissipation in different hardware blocks from the thermal infrared emissions of the processor during operation and under realistic loading conditions. When a processor runs a workload, it consumes power, which dissipates heat and changes the temperature of the chip. The thermal emissions from the chip can be captured by an infrared imaging system, and processed to reveal the underlying power consumption profile.
Post-silicon power mapping involves many challenges at both the experimental and modeling fronts. At the experimental front, it is required to control the speed and temperature of the oil flow on top of the processor to remove the generated heat, while maintaining good optical transparency to the infrared imaging systems. Furthermore, it is important to accurately synchronize all the measurements of the system, including thermal maps, fluid state measurements, total power consumption, and PMC measurements from within the processor.
At the processing front, challenges include the need to model the relationship between power consumption and temperature. This process is complicated by the fact that replacing the fan and copper heat-spreader with an infrared-transparent fluid-based heat sink system alters the thermal profile of the die. Compromised thermal characteristics will alter the leakage profile of the processor. Decomposing the total power into leakage and dynamic is a challenging task due to the dependency of leakage on process variability and temperature.
A popular approach for modeling total power is through the use of performance monitoring counters (PMCs). Performance counters are embedded in the processor to track the usage of different processor blocks. Examples of such events include the number of retired instructions, the number of cache hits, and the number of correctly predicted branches. The general approach of existing techniques is to choose a set of plausible performance counters to model the activity of each structure in the processor and then create empirical models that utilize the activities to estimate the power of each structure and the total power. In almost all existing techniques, the main way to verify the correctness is through the observation of the total power.
Power related issues in modern multi-core processors have made post-silicon power analysis a necessity in IC design flow. One of the most important factors in estimating post-silicon power is to have an accurate modeling matrix R which relates temperature to power. A modeling matrix was constructed using a laser measurements setup that injects individual powers pulses on the actual chip and measures the resultant response. In another system, a controlled test chip was to experimentally find the R-matrix by enabling each block in the test circuits. Both these methods need extensive experimental setup or special circuit design needs.
It would therefore be desirable to provide a more efficient and optimized feedback telemetry and actuation system for an integrated circuit comprising one or more mapping and modeling systems used for power estimation, management, and improved efficiencies in operation of the integrated circuit.